1. Field of the Invention
This invention relates in general to the structure and fabricating method of integrated circuit (IC), and more particularly, to the structure and fabricating method of a horn-like capacitor made by a stacked layer through a number of insulating and conductive layers alternatively superposed together in a dynamic random access memory (DRAM) device.
2. Description of Related Art
When the function of micro process is continuously enhanced and, in accordance with, the abilities of software including the program size and the computing power are increased, the capacitance of memory is enlarged accordingly. As the integration of DRAM is increased, the memory cell for the present development includes a transfer field effect transistor (TFET) and a storage capacitor. FIG. 1 is the configuration of the circuit of the memory cell in a DRAM device. In FIG. 1, the selected capacitor C, one of an array of capacitors built on the wafer, can be used to store the data by either charging or discharging the capacitor C. The most common way is that a binary data stored on a bit has a logic state of "0" as the capacitor C being discharged and has a logic state of "1" as the capacitor C being charged. In general, a dielectric thin film 102 is sandwiched between an upper electrode 100 and a lower electrode 101 of the capacitor C to provide the required dielectric constant. The capacitor C is coupled to a bit line BL and fulfills the action of read/write through charging or discharging the capacitor C by utilizing the TFET T as a switch. The action as described above is done by the following procedure that the TFET T is coupled between the bit line BL and the capacitor C through a source and a drain of the TFET T, respectively. The word line WL is coupled to the gate of TFET T to selectively control the connecting status between the bit line BL and capacitor C.
In the case of the capability of DRAM, which is less than the need for 1 Megabit in the fabricating process of an integrated circuit, the capacitance conventionally is obtained by utilizing a two dimensional capacitor, generally, called as the planar type capacitor. This kind of capacitor occupies a large area on a substrate to store the needed charges so that it is not a proper application for a high integration case. A highly integrated DRAM like one greater than 4 Megabit needs a capacitor with three dimensional structure, which has such as a stacked type or a trench type, to obtain the needed charges.
In comparison with the planar type capacitor, the stacked type or the trench type capacitor are still able to obtain a large quantity of capacitance even in the case that the size of the memory unit has been further reduced. Unfortunately a simple three dimensional structure of capacitor is no longer suited for the further highly integrated memory device having such as a DRAM with 64 Megabit.
As known by skilled persons on the fabrication of the capacitor as described above, the capacitance is decreased when the size of the memory cell has been reduced, and then the possibility of soft error is increasing due to the incident .alpha. ray on the memory cell, which has low capacitance.
One of the solutions is to extend the area of the electrode and the dielectric thin film of the capacitor horizontally and to stack them up as a type called fin type capacitor to enhance the capacitance by utilizing the increasing area size of the capacitor.
Another solution is to extend the area size of the electrode and the dielectric thin film of the capacitor vertically as a type called cylindrical type capacitor to enhance the capacitance by utilizing the increasing area size of the capacitor.
The size of a memory cell of a DRAM is continuously reduced as the integration ability is continuously increased. So, one in this field of fabricating capacitor is continuously looking for new structures and fabricating methods of the capacitor for use in semiconductor device to reduce the size but keep the capacitance.